1. Field of the Invention
The present invention generally relates to a floating gate memory device, such as a flash memory, which includes a page buffer.
2. Description of the Related Art
A memory cell transistor having a floating gate, such as a flash memory array cell, has a threshold voltage capable of being set to different levels. Both reading a state stored in the memory cell and verifying that a correct value has been programmed or erased requires that the threshold voltage of the memory cell be ascertained. To enable more rapid data access by a processor, the state of the floating gate memory cell can be stored in a page buffer.
Traditionally, memory devices use sense amplifiers and connecting reference cells configured to read or verify the state of one byte of memory cells at a time. Consequently, the read and verify operations take a great deal of time to complete for a large number of memory cells in an array. To enhance access speed, sense amplifier outputs may be provided to a page buffer. To enhance speed further, more than a byte of memory cells can be read or verified in parallel by the sense amplifiers. However, to read or verify more than one byte, the sense amplifiers and connecting circuitry required for each byte of memory cells would provide an unacceptable increase in circuitry. Memory devices providing read and verify of more than one byte in parallel without sense amplifiers are available, but do not provide acceptable accuracy.
U.S. patent application Ser. No. 08/160,582 entitled "Programmed Reference", filed Dec. 1, 1993, and incorporated herein by reference, discloses a conventional flash memory device as shown in FIG. 1 which uses sense amplifiers and reference cells to perform parallel read and verify operations on one byte of data at a time. The memory device includes a memory cell array 103. The gate of each cell in the memory array 103 is connected to one of word lines 104. The drain of each memory cell 103 is connected to one of bit lines 105.
The memory device employs a reference cell array 100 to determine the values stored in one byte of memory cells at a time. Each set of reference cells 100 includes at least three reference cells, a verify program reference cell having a threshold set for verifying a programmed state, a verify erase cell having a threshold set for verifying erase, and a read reference cell having a threshold set to determine a state stored by a memory cell.
A memory cell is considered to be programmed when its threshold voltage is raised above a set voltage, such as 4.0 volts, and erased when its threshold voltage is below a set voltage, such as 1.0 volt. To verify programming of a memory cell, with the voltage values indicated above, the drain current of the memory cell is compared with the drain current of the verify program reference cell having a threshold of 4.0 volts. The memory cell is determined to be programmed to a threshold above 4.0 volts if its drain current is less than the verify program reference cell drain current. To verify erase of a memory cell, the drain current of the memory cell is compared with the drain current of the verify erase reference cell having a threshold of 1.0 volt. The memory cell threshold is determined to be erased below 1.0 volt if its drain current is greater than the verify erase reference cell drain current. To determine the state stored by a memory cell during read, the drain current of the memory cell is compared with the drain current of a read reference cell having a threshold between the 1.0 volt and 4.0 volt working margin, such as 2.5 volts.
To enable the comparison of the drain currents of the memory cells and the reference cells as described above, each reference cell has its gate connected to a select voltage applied to the word lines 104 of the memory cells. The drains of each set of reference transistors 100 are connected to the input of multiplexer 106. Each bit line 105 of the memory array is connected to an input of a column decoder 108 that selects a byte of bit lines to its outputs. Each of the column decoder outputs is connected to a respective sense amplifier 102 first input. The output of the multiplexer 106 is connected to a second input of each of the sense amplifiers 102. Each sense amplifier 102 functions as a comparator, for comparing the drain current of each coupled bit line with the drain current of one of the reference cells. The outputs of the sense amplifiers 102 are connected to a decoder 107 which represents the output of the comparison of the sense amplifiers 102 as a digital signal.
In order to verify or read the state of more than one byte of the bit lines, additional sense amplifiers would be required in the circuit of FIG. 1. Such additional circuitry would occupy significant space on an integrated circuit which, as indicated above, is undesirable.
With the circuit of FIG. 1, the output of the decoder 107 can be provided to a page buffer to store the memory cell states for faster data access than reading each memory cell state serially through the sense amplifiers 102. To improve operation speed further, a reference Kobayashi, et al., "A 3.3 V Only 16 Mb DINOR Flash Memory", ULSI Laboratory, Mitsubishi Electric Corporation, Itami Japan, (hereinafter the Mitsubishi reference), discloses a memory device that performs read and verify operations using a page buffer directly, rather than first using sense amplifiers. The Mitsubishi reference also enables more than a byte of memory cells to be read or verified at one time.
FIG. 2 shows circuitry for the Mitsubishi reference which includes a memory array 135, similar to FIG. 1, and a page buffer, including latches 140. Although read and verify are provided directly by latches 140 of a page buffer, the Mitsubishi reference circuitry also provides connections to sense amplifiers 138 and decoders 139 similar to that shown in FIG. 1.
In the Mitsubishi reference during a read or verify operation to determine values stored in a word of memory cells, one of the word lines 142 in memory array 135 is set to a voltage approximately 1/2 Vcc. A select signal (S) connected to the gate of discharge transistor 133 is set to ground, and a precharge circuit 130 charges every even bit line in bit lines 134 to Vcc. Each odd bit line in bit lines 134 is set to ground. Once the even bit lines are charged to Vcc, the select signal is set to Vcc. Each even bit line is thereby able to be discharged to ground through a respective selected memory cell, if the memory cell has been erased to have a threshold voltage below 1/2 Vcc.
After a predetermined time, a latch enable signal is briefly applied to the gates of a set of even latch enable transistors 136. Accordingly, each even latch in latches 140 of the page buffer is switched to the state of a respective even bit line. The above process is then repeated for the odd bit lines. Even and odd bit lines are operated separately because of possible signal interference caused to a bit line by the parasitic capacitance associated with each adjacent bit line.
Although the memory device shown in FIG. 2 performs parallel read and verify operations on large numbers of memory cells, the verify and read operations may not be performed reliably with process, temperature or Vcc variations. With a variation in Vcc after programming, a voltage of 1/2 Vcc applied to the word lines of the memory cells to be read will vary, while the threshold of the memory cells remain constant. This is likely to cause a read error. Similarly, read errors are likely to be caused when the thresholds of the memory cells are altered by changes in temperature, while Vcc remains constant.
In light of the conventional art, memory designers are forced to choose between a reliable but low speed single byte read or verify circuit and the less reliable, but higher speed of the Mitsubishi reference circuit.